1 features optimized for off-line control temperature compensated oscillator 50% maximum duty-cycle clamp v ref stabilized before output stage is enabled low start-up current pulse-by-pulse current limiting improved undervoltage lockout double pulse suppression 1% trimmed bandgap reference high current totem pole output package options cs52845 current mode pwm control circuit with 50% max duty cycle cs52845 description block diagram absolute maximum ratings 10 7 14 13 12 8 1 2 3 4 5 6 11 9 comp nc v fb nc sense nc osc v ref nc v cc v cc pwr v out pwr gnd gnd 14l so narrow 1 7 8 2 3 4 5 6 comp v fb sense osc v ref v cc v out gnd 8l so narrow december, 2001 - rev. 3 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs52845 provides all the nec- essary features to implement off- line fixed frequency current-mode control with a minimum number of external components. the cs52845 incorporates a new precision temperature-controlled oscillator to minimize variations in frequency. an internal toggle flip- flop, which blanks the output every other clock cycle, limits the duty-cycle range to less than 50%. an undervoltage lockout ensures that v ref is stabilized before the output stage is enabled. in the cs52845 turn on is at 8.4v and turn off at 7.6v. other features include low start-up current, pulse-by-pulse current lim- iting, and a high-current totem pole output for driving capacitive loads, such as gate of a power mosfet. the output is low in the off state, consistent with n-channel devices. supply voltage (i cc <30ma) ..........................................................self limiting supply voltage (low impedance source)...................................................30v output current ............................................................................................... 1a output energy (capacitive load) .................................................................5 j analog inputs (v fb , v sense )...........................................................-0.3v to 5.5v error amp output sink current...............................................................10ma lead temperature soldering reflow (smd styles only) ...........60 sec. max above 183?, 230? peak v cc gnd comp osc sense v ref v ref undervoltage lockout internal bias nor s r pwm latch current sensing comparator r 2 r 1v error amplifier - + 2.50v set/ reset v cc undervoltage lock-out 34v 8.4v/7.6v r r v fb v cc pwr v out pwr gnd oscillator toggle flip-flop 5.0 volt reference
2 electrical characteristics: -40 t a 85?; v cc = 15v (note 1); r t = 10k ? ; c t = 3.3nf for sawtooth mode.unless otherwise stated. cs52845 parameter test conditions min typ max unit reference section output voltage t j =25?, i ref =1ma 4.95 5.00 5.05 v line regulation 12 v cc 25v 6 20 mv load regulation 1 i ref 20ma 6 25 mv temperature stability (note 2) 0.2 0.4 mv/? total output variation line, load, temp. (note 2) 4.90 5.10 v output noise voltage 10hz f 10khz, t j =25? (note 2) 50 v long term stability t a =125?, 1000 hrs. (note 2) 5 25 mv output short circuit t a =25? -30 -100 -180 ma oscillator section initial accuracy sawtooth mode, t j =25? 47 52 57 khz voltage stability 12 v cc 25v 0.2 1.0 % temperature stability sawtooth mode t min t a t max (note 2) 5 % amplitude v osc (peak to peak) 1.7 v error amp section input voltage v comp =2.5v 2.45 2.50 2.55 v input bias current v fb =0v -0.3 -1.0 a a vol 2 v out 4v 65 90 db unity gain bandwidth (note 2) 0.7 1.0 mhz psrr 12 v cc 25v 60 70 db output sink current v fb =2.7v, v comp =1.1v 2 6 ma output source current v fb =2.3v, v comp =5v -0.5 -0.8 ma v out high v fb =2.3v, r l =15k ? to gnd 5 6 v v out low v fb =2.7v, r l =15k ? to v ref 0.7 1.1 v current sense section gain (notes 3 & 4) 2.85 3.00 3.15 v/v maximum input signal v comp =5v (note 3) 0.9 1.0 1.1 v psrr 12 v cc 25v (note 3) 70 db input bias current v sense =0v -2 -10 a delay to output t j =25? (note 2) 150 300 ns output section output low level i sink =20ma 0.1 0.4 v i sink =200ma 1.5 2.2 v output high level i source =20ma 13.0 13.5 v i source =200ma 12.0 13.5 v rise time t j =25?, c l =1nf (note 2) 50 150 ns fall time t j =25?, c l =1nf (note 2) 50 150 ns
3 package pin description package pin # pin symbol function electrical characteristics: unless otherwise stated, specifications apply for -40 t a 85?; v cc = 15v (note 1); r t = 10k ? ; c t = 3.3nf for sawtooth mode. parameter test conditions min typ max unit total standby current start-up current 0.5 1.0 ma operating supply current v fb =v sense =0v r t =10k ? , c t =3.3nf 11 17 ma v cc zener voltage i cc =25ma 34 v pwm section maximum duty cycle 46 48 50 % minimum duty cycle 0 % undervoltage lockout section start threshold 7.8 8.4 9.0 v min. operating voltage after turn on 7.0 7.6 8.2 v notes: 1. adjust v cc above the start threshold before setting at 15v. 3. parameter measured at trip point of latch with v fb =0. 2.these parameters, although guaranteed, are not 100% tested in production. 4. gain defined as: a = ; 0 v sense 0.8v. ? v comp ? v sense 8l 14l so narrow so narrow 1 1 comp error amp output, used to compensate error amplifier. 23 v fb error amp inverting input. 3 5 sense noninverting input to current sense comparator. 4 7 osc oscillator timing network with capacitor to ground, resistor to v ref . 5 9 gnd ground. 5 8 pwr gnd output driver ground. 610v out output drive pin. 711v cc pwr output driver positive supply. 712v cc positive power supply. 814v ref output of 5v internal reference. 2,4,6,13 nc no connection. cs52845
undervoltage lockout during undervoltage lockout (figure 1), the output driv- er is biased to sink minor amounts of current. the output should be shunted to ground with a resistor to prevent activating the power switch with extraneous leakage cur- rents. pwm waveform to generate the pwm waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (figure 2). an increase in v cc causes the inductor current slope to increase, thus reducing the duty cycle. this is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. when the power supply sees a sudden large output cur- rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. since the duty cycle tends to exceed the maximum allowed to prevent transformer saturation in some power supplies, the inter- nal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of osc compo- nents. 4 figure 1: startup voltage for the cs52845. circuit description test circuit open loop laboratory test fixture v ref v cc v out 1k ? 1w 0.1 f 0.1 f v ref v cc v out gnd v fb sense osc comp 5k ? 100k ? 4.7k ? 1k ? error amp adjust 4.7k ? sense adjust r t 2n2222 c t gnd a v cc v on = 8.4v v off = 7.6v on/off command to reset of ic <15ma <1ma v on v off i cc v cc cs52845
setting the oscillator the times t c and t d can be determined as follows: grounding high peak currents associated with capacitive loads neces- sitate careful grounding techniques. timing and bypass capacitors should be connected close to gnd in a single point ground. the transistor and 5k ? potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to sense. 5 cs52845 v upper v lower t on t off t c t d t on =t c t off =t c +2t d circuit description:: continued substituting in typical values for the parameters in the above formulas: v ref = 5.0v, v upper = 2.7v, v lower = 1.0v, i d = 8.3ma, then t c 0.5534r t c t t d = r t c t ln for better accuracy r t should be 10k ? . ) 2.3 - 0.0083 r t 4.0 - 0.0083 r t ( v cc i o v o switch current ea output toggle f/f output osc reset v osc figure 2: timing diagram figure 3: duty cycle parameters. t c = r t c t ln t d = r t c t ln ) v ref - i d r t - v lower v ref - i d r t - v upper ( ) v ref - v lower v ref - v upper (
6 cs52845 d lead count metric english max min max min 8l so narrow 5.00 4.80 .197 .189 14l so narrow 8.75 8.55 .344 .337 thermal data 8l 14l so narrow so narrow r jc typ 45 30 c/w r ja typ 165 125 ?/w package specification package dimensions in mm (inches) package thermal data ordering information part number description cs52845ed8 8l so narrow cs52845edr8 8l so narrow (tape & reel) cs52845ed14 14l so narrow cs52845edr14 14l so narrow (tape & reel) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design 1.27 (.050) bsc 0.51 (.020) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) d 0.25 (0.10) 0.10 (.004) 1.75 (.069) max 1.27 (.050) 0.40 (.016) ref: jedec ms-012 0.25 (.010) 0.19 (.008) surface mount narrow body (d); 150 mil wide
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